Aspects of semiconductor fabrication technology have focused on achieving highly integrated devices. In semiconductor memory devices, one frequently studied device is a nonvolatile silicon oxide nitride oxide silicon (SONOS) memory device. A difference between a SONOS device and a flash memory device is that, in a structural viewpoint, the flash memory device stores charges using a floating gate whereas the SONOS device stores charges in a nitride layer. Such a SONOS semiconductor device may include a memory region for storing charges and a logic region constituting a peripheral circuit. The memory region is defined on and/or over an oxide nitride oxide (ONO) layer including a nitride layer enabling charge trapping. The logic region is defined on and/or over a silicon oxide (SiO2) layer as gate dielectrics.
In a method for manufacturing a SONOS semiconductor device, a device isolation layer is first formed on and/or over a silicon (Si) semiconductor substrate to divide a memory region and logic region from each other. In addition, to divide the logic region into a plurality of regions, a plurality of device isolation layers are formed. The logic region may include an ultra-high voltage region (Ultra V), a high voltage region (High V) and a low voltage region (Low V). Of the plurality of regions divided by the device isolation layers, an ONO layer, which includes a first oxide layer, a nitride layer and a second oxide layer, is formed only on and/or over the memory region.
The ONO layer is formed on and/or over the memory region via patterning using a first photoresist pattern. The first photoresist pattern is removed via etching and cleaning processes. Next, a first gate oxide layer, which may be composed of silicon oxide (SiO2) is formed only on and/or over the memory region and the ultra-high voltage region (Ultra V) of the logic region. The first gate oxide layer is formed on and/or over the memory region and the ultra-high voltage region (Ultra V) via patterning using a second photoresist pattern. The second photoresist pattern is removed via etching and cleaning processes. Next, a second gate oxide layer, which may be composed of silicon oxide (SiO2), is formed only on and/or over the high voltage region (High V) of the logic region. The second gate oxide layer is formed on and/or over the high voltage region (High V) via patterning using a third photoresist pattern. The third photoresist pattern is removed via etching and cleaning processes. Thereafter, silicon oxide (SiO2) is deposited to form a third gate oxide layer on and/or over the entire surface of the semiconductor substrate.
In such a method for manufacturing a SONOS semiconductor device, the processes for forming the ONO layer on and/or over the memory region and forming several gate oxide layers on and/or over the logic region require three separate mask processes. Meaning, forming the gate oxide layers on and/or over the ultra-high voltage region, the high voltage region and the low voltage region of the logic region, three separate mask processes are implemented. Accordingly, the overall manufacturing time is undesirably long, resulting in poor manufacturing efficiency. Further, the additional number of manufacturing processes also increases overall manufacturing costs.